1. Field of Invention
This invention relates to digital-to-analog converters embodied in semiconductor integrated circuitry. In particular, this invention relates to a digital-to-analog converter (DAC) circuit adapted for simple, accurate and stable compensation of an analog output signal to conform with input binary number values.
A DAC has a variety of applications permitting the interchange of information between an analog environment of continuously variable parameters and a digital environment of discrete parameter values. A DAC is useful for producing a predictable analog signal level from a specified digital value represented by a set of binary-valued signals. The sum of currents, for example, digitally switched in parallel may determine the analog output signal value. One of the persistent problems associated with a DAC, particularly a DAC fabricated in an integrated circuit, is precision of calibration. Ideally, the analog output value of a DAC should correspond to its digital input value within one half part of the least significant bit (1/2 LSB) throughout the entire range of operation of the device. In a device having a 12-bit range, the accuracy of calibration is ideally at least one part in 2.sup.13. Analog circuitry having that degree of precision is not readily fabricated.
Integrated circuit fabrication has both advantages and disadvantages in the construction of a DAC. For example, it is possible to fabricate an integrated DAC having parameters which remain substantially stable relative to one another over a range of operating conditions. However, absolute parameters of integrated DACs may differ relative to one another, requiring trimming to bring the device into compliance with the desired degree of linearity. It is therefore desirable to provide a mechanism for compensating for fabrication uncertainties.
FIG. 1 illustrates one desired type of compensation, herein designated segment or MSB (for most significant bit) compensation. In MSB compensation, the mechanism provides for correction of selected most significant bits. The number of bits of correction depends on the maximum chosen size of the supporting memory. MSB compensation permits precisely calibrated encoding of digital data of the more significant bits wherever lesser significant bits have zero value. Therefore, MSB compensation provides an accurate baseline for higher precision compensation. For example, in a 12-bit device, the data format is XXXX00000000, where the four leading bits are the bit values defining an MSB code which determines the stepwise transition. FIG. 1 illustrates both the uncompensated and the compensated transfer characteristic for MSB compensation.
FIG. 2 illustrates a second and different type of compensation, herein designated LSB (for least significant bit) interpolation compensation, since it involves interpolation between consecutive MSB codes. In this technique, it is desired that the lesser significant bits align precisely with the slope between transitions of the greater significant bits. For example, in a 12-bit device, data of the format ABC011111111 must produce an analog output differing by 1.+-.1/2 LSB from the analog output produced by data of the format ABC100000000 (where A, B and C are arbitrary binary values of the more significant bits). Absent such alignment, there will be significant and noticeable non-linearities. FIG. 2 illustrates both the uncompensated and the compensated transfer characteristic for LSB compensation.
In the past, LSB compensation has generally not been capable of providing non-uniform compensation as between consecutive MSB codes over the range of MSB values. In the typical prior art fabrication technique, a DAC is fabricated to provide an uncompensated output initially different from that desired. Compensation has been generally effected by cutting or trimming material from the circuit die with a laser, by cleaving fusible links, or by forcing large reverse currents through protection diodes to cause diode breakdown. Each of these techniques is intended to alter the analog current-carrying characteristic of bit-setting resistors. However, such techniques initially require a relatively large on-chip component area, specially designed equipment, and long trim time. In addition, such techniques generally are impractical after the device is packaged and burned in.
The inherent problems of on-chip analog compensation, such as laser trimming, have been recognized in the prior art. Specifically, an alternative technique has been suggested for segment compensation. The alternative technique involves the use of a Programmable Read Only Memory element (PROM) to control digitally current carrying elements. A monolithic 14-bit DAC manufactured under the designation ICL7134 by Intersil, Inc. of Cupertino, Calif. incorporates this technique. This device is illustrated in FIG. 3 and is described for example in Brubaker et al., "14-Bit DAC Mates With Microprocessors, Settles in Less Than 1 Microsecond." Electronic Design, Apr. 16, 1981, Page 147. In the ICL7134, there are provided multiple DACs on chip, an output DAC and a compensating DAC. The five most significant bits of the output DAC are compensated as in FIG. 1 herein by the programming of a PROM with correction codes which control the output of the compensating DAC. The scale factor is constant and the scale factor error cannot be corrected as between consecutive MSB codes. Thus the scale factor error is mapped though all MSB values. PROM programming involves the selection of one correction code for each combination of the most significant bits. FIG. 3 herein is a reproduction of a functional block diagram of the ICL7134 DAC from the cited article.
Other background on digital error correction is found in Prazak et al., "Correcting Errors Digitally in Data Acquisition and Control," Electronics, Nov. 22, 1979, Page 123. Some types of DACs not to be confused with the present invention are of a design which is not conducive to compensation. A patent of interest is Schoeff, U.S. Pat. No. 4,292,625 issued Sept. 29, 1981. The '625 patent describes a DAC having a segment generator for the more significant bits and a step generator for the lesser significant bits wherein the problem of segment carry is addressed. No trim type compensation is employed.
Other publications relating to the problems of calibration are Schoeff, "An Inherently Monotonic 12b DAC", 1979 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Page 178, and Schoeff, "An Inherently Monotonic 12 Bit DAC", IEEE Journal of Solid-State Circuits, Volume SC-14 (December 1979), Page 904.